The present invention relates generally to phase-locked loop (PLL) circuits. More particularly, the present invention relates to methods and circuitry for compensating for propagation delay through the phase comparator of a PLL circuit.
PLL circuits are a type of control loop that controls the phase of a number of signals. PLL circuits are implemented in a wide variety of electronic devices including electronic test equipment. The basic design and characteristics of PLL circuits are well established and known in the art.
FIG. 1 shows a block diagram of a typical PLL circuit in accordance with the prior art. The PLL circuit 100, shown in FIG. 1, includes four basic components: a phase comparator (phase detector) 105, a loop filter 110, a voltage controlled oscillator (VCO) 115, and a clock divider (frequency divider) 120. The components are connected in a feedback configuration as shown in FIG. 1. The phase detector 105 compares the phase of the input reference clock signal 102 with the phase of the feedback VCO signal 108 and provides a DC output signal 103 proportional to the phase difference of the two signals. The VCO circuit generates a frequency proportional to its input voltage. The output voltage of the phase detector 105 is used to adjust the VCO 115 until the difference in phase between the two signals is very small.
However, as the frequency of the input reference clock signal 102 changes, the propagation delay through the phase detector 105 changes. This changes the phase relationship between the input reference clock signal 102 and the output clock signal 107. The propagation delay may only be on the order of tens of picoseconds (ps), but this may have significant detrimental effect in applications requiring highly accurate timing such as electronic test equipment.
Moreover, the change in propagation delay as a function of frequency is not the same from one PLL circuit chip to the next. In applications employing multiple PLL circuits and variable frequencies (e.g., electronic test equipment), the change in propagation delay may have a serious detrimental effect on the timing calibration.
It is possible to compensate for the propagation delay through the phase detector by adjusting a tuning voltage to tune the VCO circuit. As shown in FIG. 1, the phase detector output signal 103 is summed with signal 104 at a current summing node. By varying the resistance tied to the tuning voltage, the current of signal 104 can be changed. Typically, each VCO is connected to an oscilloscope and resistance values are substituted to tune the reference voltage until the phase difference between the input reference clock signal and the output clock signal is near zero. This is a costly and time consuming process and is imprecise as it is dependent upon ambient conditions and subject to operator error.
Phase detectors that are less sensitive to frequency variation could be developed, but because the variation of propagation delay with frequency is relevant in only a small number of applications, there is no pressure on manufacturers to produce a less sensitive PLL circuit chip.
Additionally, as typical clock frequencies continue to rise there will be a corresponding rise in the accuracy required of the PLL circuit. At higher frequencies the PLL circuit will be more sensitive to the errors caused by the phase detector propagation delay. This will make conventional tuning methods more complex and costly while manufacturers will be less likely to pursue the ideal PLL circuit chip.
A digitally tunable phase-locked loop (PLL) circuit is described. A progammable digital-to-analog converter (DAC) is coupled to the PLL circuit such that the output voltage of the DAC may be used as a tuning voltage for the PLL circuit.